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  new product r03ds0013ej0100 rev.1.00 2011.09.05 page 1 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 8-bit 2ch d/a converter wit h buffer amplifiers for i 2 c bus (corresponds to fast mode) R2A20152NS/sp description the r2a20152 is an integrated circuit semiconductor of cmos structure with 2 channels of built in d/a converters with output buffer operational amplifiers. it is the characteristic improvement version of m62332. the input interface is i 2 c bus serial data method, and connects with a microcomputer with minimum wiring. it conforms fast-mode of i 2 c bus specifications. the output circuit is composed of buffer operational amplifier with sync and source drive capacity of 1.0 ma or more, and it operates in the whole voltage range from vcc to ground. features ? guarantee differential nonlinearity error : +/-0.7lsb, nonlinearity error : +/-1.0lsb ? digital data transfer format: i 2 c bus serial data method (corresponds to fast mode: 400khz) ? output buffer operational amplifier: it operates in the whole voltage range from vcc to ground. ? high output current drive capacity: +/-1.0 ma over ? very small size son-8 package application conversion from digital data to analog control data for home-use and industrial equipment. signal gain control or automatic adjustment of lcd-tv, pdp-tv, lcd-monitor, or etc. blurring correction control or various control of the interchangeable lens of digital camera. block diagram 8 7 6 5 1 2 3 4 i 2 c bus tranceiver channel decoder 8-bit latch + + power on reset 8-bit latch vcc scl sda gnd ao1 ao2 n.c. n.c 8-bit upper segment r-2r 8-bit upper segment r-2r
new product R2A20152NS/sp page 2 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 pin arrangement pin description not connected n.c. 3 n.c. 4 gnd terminal gnd 5 8-bit resolution d-a converter output terminal (after power on, analog output of ev ery channel is set in dac data "00h") ao1 1 ao2 2 power supply terminal vcc 8 serial clock input terminal scl 7 serial data input terminal sda 6 function pin name pin no. outline: prsp0008de-c (sop-8) [sp] r2a20152sp 1 2 3 4 8 7 6 5 (top view) ao1 ao2 n.c. n.c. vcc scl sda gnd n.c. : not connected outline: pwsn0008ka-a (son-8) [ns] R2A20152NS 1 2 3 4 8 7 6 5 (top view) ao1 ao2 n.c. n.c. vcc scl sda gnd n.c. : not connected
new product R2A20152NS/sp page 3 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 (vcc= +5v +/-10%, gnd=0v, ta= -30 to +85deg, unless otherwise noted) v 1.9 1.5 - vcc = 0 to 2.7v vcc por internal reset operating voltage *1 s -- 100 vcc = 0 to 2.7v tr vcc rise time of supply voltage *1 ms --1 vcc < 0.1v t por power supply restart interval (power supply off ? on) *1 ma 1.5 0.5 0 clk = 500khz, i ao = 0a, data: 6ah (at maximum current) ma 1.0 - -1.0 upper side saturation voltage = 0.3v, lower side saturation voltage = 0.2v i ao buffer amplifier output drive range ns 50 -0 t sp pulse width of spike noise v- 0.8 0.5 vhys hysteresis of schmitt trigger input (sda, scl) v 0.4 -- isink =3ma v ol output low voltage (sda) vcc = 5.12v (20mv/lsb), without load ( i ao = 0a ) i ao = 500a i ao = 100a v in = 0 to vcc sda = scl = gnd, i ao = 0a test condition r o c o s full s zero s l s dl v ao vi h v il i ilk icc vcc symbol lsb 2.0 - -2.0 zero code error ohm - 5.0 - buffer amplifier output impedance vcc ? 0.2 - 0.2 v vcc ? 0.1 - 0.1 buffer amplifier output voltage range lsb 1.0 - -1.0 nonlinearity a 10 - -10 input leak current v 0.2vcc -0 input low voltage v vcc - 0.8vcc input high voltage lsb 0.7 - -0.7 differential nonlinearity lsb 2.0 - -2.0 full scale error f 0.1 -- output capacitate load ma 1.0 0.3 0 supply current v 5.5 5.0 2.7 supply voltage max. typ. min. unit ratings item ta > +25deg ta = +85deg continuous condition mw/deg 6.75(ns) / 6.8(sp) k theta thermal derating factor ma -2.0 to +2.0 i ao buffer amp. output current tstg topr pd vo vin vcc symbol v -0.3 to vcc+0.3 < +6.5 output voltage mw 270(ns) / 272(sp) power dissipation deg -40 to +125 storage temperature deg -30 to +85 operating temperature v -0.3 to vcc+0.3 < +6.5 input voltage v -0.3 to +6.5 supply voltage unit ratings item absolute maximum ratings electrical characteristics *1 : when power supply is turned on, internal circuit is initia lized by power on reset circuit. but, if re-powered on quickly, initialize is not operate. so, k eep the time period of re-powered on (t por ). vcc internal reset signal t por tr vcc < 0.1v (equivalent to tr vcc ) vcc por resetting period gnd gnd resetting period ta= 25deg, unless otherwise noted)
new product R2A20152NS/sp page 4 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 c b t su:sto t f t r t su:dat t hd:dat t su:sta t high t low t hd:sta t buf f scl symbol max. min. - 4.0 - - 250 0 4.7 4.0 4.7 4.0 4.7 0 standard mode 400 - 300 1000 - 3.45 - - - - - 100 s - 0.6 set-up time for a repeated start condition ns 300 - fall time of both sda and scl signals s - 0.6 high period of the scl clock s - 1.3 low period of the scl clock khz 400 0 scl clock frequency s - 1.3 time the bus must be free before a new transmission can start s - 0.6 hold time (repeated) start condition after this period, the first clock pulse is generated. s 0.9 0 data hold time pf 400 - capacitive load of bus line ns 300 - rise time of both sda and scl signals s - 0.6 set-up time for stop condition ns - 100 data set-up time max. min. unit fast mode item above values correspond with input level (v ih min / v il max). timing chart sda v ih v il scl v ih v il start start start stop t r , t f t buf t hd:sta t su:dat t hd:dat t su:sto t low t su:sta t high i 2 c bus line characteristics
new product R2A20152NS/sp page 5 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 i 2 c bus format sta stp a a aw slave address sub address dac data note: sta: start condition, w: write (sda = low), a: acknowledge bit, stp: stop condition 10 11001 ? slave address first last xxs0 xxxxx ? sub address first last channel select data ch2 selection 1 ch1 selection 0 channel selection s0 don?t care channel select data d2 d1 d0 d3d4d5d6d7 ? dac data first msb last lsb 1 1 : 1 1 0 0 d1 vcc / 256 x 3 0 000000 vcc 1 111111 vcc / 256 x 255 0 111111 : : :::::: vcc / 256 x 4 1 000000 vcc / 256 x 2 1 000000 vcc / 256 x 1 0 000000 dac output d0 d2d3d4d5d6d7 first msb last lsb
new product R2A20152NS/sp page 6 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 data timing chart scl and sda (model) < start condition to sleve address bit > sda scl d/a output < sub address bit > sda scl d/a output start condition 1234 56 7 w a 1234 56 7 8 a sda scl d/a output 1234 56 7 8 a < dac data bit to stop condition > stop condition ? start condition with scl at high, sda goes from high to low. ? stop condition with scl at high, sda goes from low to high. ( under normal condition, sda must be changed, when scl is low. ) ? acknowledge bit the receiving ic has to pull down sda line whenever receive slave data (transmitting ic releases the sda line just then transmit 8-bit data.)
new product R2A20152NS/sp page 7 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 digital data formats a dac data 1 a sub address 1 aw slave address sta a dac data 2 a sub address 2 sub address n stp a dac data n a note: after start condition, the master ic (mcu etc.) accesses the slave ic by slave address, and transmits the data to each channel by two bytes (sub address and dac data). precaution for use 1. supply voltage terminal (vcc) is also used for d/a converter upper reference voltage setting. if ripple or spike is input this terminal, accuracy of d/a conversion is down. so, when use this device, please connect capacitor among vcc to gnd for stable d/a conversion. 2. this ic?s output amplifier has an advantage to c apacitive load. so it?s no problem at device action when the capacitor (0.1f max) is connected among output to gnd for every noise elimination. standard application circuit 1 2 3 4 8 7 6 5 analog output terminals + 10? f mcu 5v 5v R2A20152NS/sp vcc scl sda gnd n.c n.c ao2 ao1 ordering information embossed taping/2,500 pcs. sp prsp0008de-c sop-8 r2a20152sp embossed taping/5,000 pcs. ns pwsn0008ka-a son-8 R2A20152NS packing/quantity package type no. package code package name order part no.
new product R2A20152NS/sp page 8 of 8 r03ds0013ej0100 rev.1.00 2011.09.05 package dimensions pwsn0008ka-a [ns] prsp0008de-c [sp]
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. 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